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Original Date: 01/24/1994
Revision Date: 01/18/2007
Best Practice : Best Modeling Practices
Because companies in the semiconductor industry rely on bringing new products quickly to market to remain competitive, there is a constant effort to reduce the product-to-market cycle time. One critical component to reducing this cycle time is the application and improvement of computer-aided design tools and their related models that provide the basis for circuit simulation and verification. To improve the overall product-to-market cycle times and manufacturability of its end products, Harris initiated development, delivery, and continuous improvement of the SPICE models and modeling systems.
The Harris Modeling Team was tasked with delivering Revision X models (Revision 0 through Revision 3) for existing and new processes (technologies) according to resource commitments, customer priorities, and maps defining what was desired, commonly referred to as Should-Be Maps; implementing the Should-Be Modeling Maps and procedures for new and existing processes; and ensuring the modeling maintenance map is implemented.
The enhanced design process resulting from this effort included the use of fabrication data, parametric data gathered during wafer testing, and modification and improvement of SPICE models. This practice was directly applicable to Harris Semiconductor's market strategy that focused on analog and mixed signal circuits whose yields are determined more by parametric properties than defect densities.
Computer-aided design modeling and Monte Carlo simulations at Harris now use statistically-based data such as a parameter's mean and standard deviation versus the nominal. This practice prevents blindly placing a certain percentage tolerance around a nominal for worst case studies when there is no data to support that tolerance. Model predictions are more accurate using parametric data. First time success of a new product and continued high yields therefore become commonplace. Two technologies whose models are advanced in the model rating criteria, but not yet at the highest criteria, have been used by Harris engineers and customers for analog ASIC designs. They achieved a 100% first-pass success rate, 26 of 26, versus a more traditional 20% success rate.
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