Original Date: 01/24/1994
Revision Date: 01/18/2007
Information : Design for Reliability
Harris Semiconductor has initiated a program focused on designing for reliability. The traditional approach emphasized screening or testing reliability after the process/product concept had been initiated. This approach placed a high risk on process qualification as well as product characterization.
The Harris Design for Reliability program accounts for key semiconductor manufacturing trends that forecast shrinking product geometries such as 0.25-micron channels, 60 Angstrom gate oxides, 0.35-micron lines and 0.5-micron spaces by the year 2000. The geometries raise new issues regarding processing defect densities, current densities and electromigration. This is further compounded by an increasing difficulty in measuring product reliability to the expected evolution of product failure rates from 1000 failures/108 hours (FIT) to 10 FITs. This decrease in product FIT rates necessitates two orders of magnitude increase in device samples if conventional reliability prediction approaches are used. In some cases it could require cost prohibitive and wasteful sampling population increases. The Harris program minimizes samples and risk by implementing accelerated stress techniques at the wafer level that address device wear out and defects, and using a paradigm shift to reliability considered at the concept and process definition phases as opposed to later in the process at product qualification and package interaction.
Reliability considerations are now addressed at the product kickoff phase and are again covered at concept development and design phases. Early considerations include testing on electromigration characterization and structures, voltage ramp breakdown structures, hot carrier stress, device stability, and thin oxides. When major changes are made to existing processes, a requalification process is employed which focuses on reliability issues. The utilization of drop-in test structures and wafer-level accelerated test make this an economical and timely approach. The wafer-level accelerated test can evaluate wear-out mechanisms in ten seconds to one minute. These tests offer qualitative comparisons between processes and help reduce development time and increase reliability confidence for new or modified processes. These efforts have been one of several contributors to the corporate goal of decreasing the product-to-market time as evidenced by a change from 127 weeks in 1987 to 60 weeks in 1993.
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