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Original Date: 04/20/1998
Revision Date: 01/18/2007
Information : Defect Analysis Team
Several years ago, the Circuit Card Assembly area experienced recurring defects. In response, ITT Aerospace/ Communications Division established the Defect Analysis Team (DAT) as a governing body to assure in-circuit yield improvements. This cross-functional team consists of production, manufacturing, and quality engineering personnel.
The DAT set up a four-level defect pareto analysis based on in-circuit yields: Level One is In-Circuit Yield History, consisting of all boards; Level Two is In-Circuit Defect Trends, broken down by assemblies, components, solder, and miscellaneous; Level Three is a break-down of each level two attribute; and Level Four is a listing of all defects. The DAT Root Cause Corrective Actions are based on the worst yielding assemblies according to the defect pareto analysis.
Through the DAT’s efforts, ITT Aerospace/Communications Division (A/CD) established or changed several processes which reduced the number of defects. This approach is an important tool used by the company in reaching its goal of first-time test yield improvements.
For more information see the
Point of Contact for this survey.
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