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Original Date: 08/20/2001
Revision Date: 12/14/2006
Best Practice : Embedded, Commercial-off-the-Shelf, Digital Signal Processor Benchmarking, Sizing, and Simulation
Lockheed Martin Naval Electronics & Surveillance Systems-Surface Systems facilitated a move from proprietary hardware to commercial-off-the-shelf hardware for complex radar systems by introducing an iterative design, test, and simulation process. This process provides benefits in scalability, platform independence, program schedules, and costs.
In the past for very technically complex radar systems, Lockheed Martin Naval Electronics & Surveillance Systems- Surface Systems (NE&SS-SS) designed and built proprietary hardware components in-house, which were combined to construct digital signal processors (DSPs). While the proprietary hardware scheme fulfilled the stringent performance requirements, the cost was higher than tolerable in a commercial-off-the-shelf (COTS) era. Because many proprietary hardware elements were unique, these elements often required dedicated customized software. This very rigid hardware/software architecture led to a rigidly sequential design-and-test process. Many hardware elements and their supporting software had to be built, tested, and fully analyzed before another hardware/software set could be designed and/or tested. As a result, the design cycle was stretched out; no software performance measurements were possible early-on; and all meaningful system testing occurred late in the program schedule where changes are costly. In response, Lockheed Martin NE&SS-SS developed an iterative design and test regime for embedded COTS DSPs that identifies risk early and saves time and money.
In the Embedded COTS DSP Benchmarking, Sizing, and Simulation regime, the design test and simulation process is iterative. The process employs COTS hardware, and the software design uses standard C-Language Application Program Interfaces (APIs). Embedded refers to accessing COTS hardware at the API level. Since the hardware has uniform COTS elements, its behavior is well known and predictable. Similarly, the interface of the software with the hardware through standard APIs is uniform and predictable. Therefore, design engineers take advantage of these traits to “build a little, test a little” and focus on the overall system performance, rather than the details of unique hardware/software pairings. Numerous other benefits arise from this process. Designs are easily scalable since the crucial computational software algorithms can be written to take advantage of standard APIs and uniform hardware.
A C-Language simulator can examine the impact of input/output operations on a full-scale DSP fairly early-on. The design is platform independent, as different vendors’ COTS hardware elements are typically interchangeable to adhere to performance and interface requirements. The iterations of the process are:
Iteration 0 - Benchmarks established by vendor at vendor site.
Iteration 1- Initial simplified software algorithms designed and tested on scaled-down DSP.
Iteration 2 - Full software algorithms designed and tested on scaled-down DSP.
Iteration 3 - Optimization for initial release on full DSP.
Iteration 4 through N - Incremental functionality designed and tested.
Since the Embedded COTS DSP Benchmarking, Sizing, and Simulation regime was implemented, the primary savings to Lockheed Martin NE&SS-SS is time. Because productive design starts immediately, the design cycle is now shortened. By catching software errors early-on, the high costs of correcting software later in coding are minimized. Another benefit is early identification of problems in the design and test stages, which leads to a higher confidence in risk estimations. Because the hardware and software elements are fairly uniform and scalable, the company can be more confident that the risks identified early will be representative of risks identified later.
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