Original Date: 09/14/1998
Revision Date: 01/18/2007

The test engineers and circuit/product designers at Raytheon Missile Systems Company’s (RMSC’s) Electronic and Product Design Center work concurrently during the early stages of product design to maximize usage of new digital design testability and test techniques. The Center’s latest technique is the Boundary Scan Test (BST), which combines digital circuit design, design for test/testability, and prototype test functions. The BST enables users to employ PC-based assembly verification tests and in-system/on-board programmable capabilities for new designs. Typical programming scenarios include setting up devices (e.g., logic chips, field-programmable gate arrays) with simulation vectors for low speed verification of design simulation in hardware or with synthesized test bench parameters to apply stimulus to a Unit Under Test (UUT) at speed.

The BST function must be designed into a new digital design as a resident part of the microchip circuit. This process involves using the designer’s circuit database; completing post processing of the board netlist to a PC platform; applying Boundary Scan Descriptive Language models for compilation; and creating support files via commercial- off-the-shelf (COTS) software tools. Technicians can apply the BST to a UUT by using a Windows 95-based PC, a COTS controller card, and RMSC-designed controller software. The BST provides complete testing capability which can be quickly implemented and placed on-line to test a product’s first engineering units. This same test software and test platform can be used in other settings (e.g., engineering laboratory, circuit board assembly facility, production test and rework facility), which significantly reduces costs and improves efficiencies.

RMSC successfully implemented BST practices on its Standard Missile Block IV and AIM-9X programs, which reduced troubleshooting cycle times by a factor of 8:1. Other benefits include eliminating $1.5 million in capital equipment costs and $35,000 in annual recurring costs for automated test system operations; setting up two new digital designs that are 100% in-circuit programmable; and establishing cost effective PC-based circuit ring-out (shorts and opens) in new digital designs.

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