|
Original Date: 05/01/1992
Revision Date: 01/18/2007
Information : VHDL Aids ASIC Development
Texas Instrument/Semiconductor Group/Military Products (TI/SG/MP) has incorporated IEEE 1076 VHDL into its ASIC design process. VHDL is a language that describes the behavior of a device, and that description may consist of a behavioral (Boolean) or a structural netlist.
TI/SG/MP provides VHDL libraries and other design tools to help them model a design for customers interested in purchasing ASICs. Current TI/SG/MP military ASIC VHDL design tools support the following: Simulation -- Mentor QuickHDL and Cadence Leapfrog; Synthesis -- SYNOPSYS Design CoMPDiler and Static Timing Analysis -- View Logic motive and SYNOPSYS Primetime.
TI/SG/MP VHDL design flow is shown in the attached graphic. A behavioral VHDL netlist or a captured schematic is first input into the SYNOPSYS synthesis coMPDiler. The coMPDiler can generate a netlist from a VHDL description. Using TI/SG/MP library, the coMPDiler generates a VHDL structural netlist. This netlist, in combination with user generated stimuli, is given to the simulator for processing. The simulator generates the expected output of the module.
Test vectors, to verify the silicon, are developed via the simulator output. Together, the VHDL structural netlist and test vectors are handed off to TI/SG/MP for manufacture and test of the silicon. TI/SG/MP currently uses TI-built V-Series ASIC testers at the Midland site for prototype and production and testing of military ASICs. TI/SG/MP has a dedicated on-site ASIC team consisting of Marketing, Design Support Engineering, Product/Test Engineering, Planning, and Quality Assurance personnel to support VHDL-based design.
VHDL Design Flow
For more information see the
Point of Contact for this survey.
|
