Despite the noted lack of adequate formal methods for testability demonstration, analytical techniques are available for specific technologies at specific levels of design. In particular, fault simulation tools have been used for several years in the assessment of digital designs. They are used at the IC level for manufacturing level test, and at the circuit card level and above for both manufacturing level test and diagnosis for repair.
In general, simulation, as described here, is the process of modeling the behavior of an object. The purpose of using simulation is to save costs by verifying the designs and their specifications in a software environment, prior to committing the design to hardware. Fault simulation of a digital network is the modeling of the network's behavior in the presence of faults, where such faults can be caused by physical defects or environmental influences.
As a means of testability verification, fault simulation is used for measuring or grading the adequacy of a set of test patterns for detecting single "stuck-at" faults. In this way, the percentage of failures that are detectable in the circuit, given a specific test pattern, is reported by a particular fault simulation package. In essence, this is a measure of the fault coverage capability of the test pattern. Fault coverage is measured as the ratio of the number of faults detected by the test pattern to the total number of simulated faults. Note that this number is not always determined the same way in all fault simulators9 . For instance, some fault simulators determine
the number of "fault classes" detected by the test pattern and divide this by
the total number of fault classes simulated to get fault coverage. A fault
class is one or more faults in a circuit that cause the same fault signature
at a primary output of the circuit. Note also that most fault simulators
simulate "Stuck at" faults on the inputs and outputs of the devices in the
model. This is the most popular fault model, and will represent a majority of
the faulty behaviors of digital circuits. However, this technique does not
cover all possible faults, and therefore some faults can still occur that are
undetectable, even if the fault simulation results in 100% fault coverage. The
standard procedure for fault coverage measurement, procedure 5012 of
MIL-STD-883, outlines a method for obtaining consistent results from any
commercially available fault simulator. This procedure is provided in Section
of this appendix.
Note that the achievable level of fault coverage is determined by the design of the circuitry, and not just the test patterns. Many commercial packages that provide fault simulation capabilities also report design characteristics that contribute to poor fault coverage values, thus allowing the design engineer to make changes necessary to improve the testability of the circuit.
In addition to identifying design characteristics that inhibit fault coverage potential, many fault simulators are used to build fault dictionaries for the purpose of fault isolation. Fault dictionaries are created by applying tests to the design and then recording the errors in the form of a fault signature. When an actual test is applied using ATE, for example, the errors that result are recorded, and the fault dictionary is then searched in order to find the fault signature that matches the observed fault signature. The corresponding list of candidate faults represents the ambiguity groups that may contain the fault. Note that creation of such fault dictionaries, especially for highly complex designs, can be expensive. Because of this, fault simulation is used more to evaluate the fault detection characteristics of the design, rather than to build fault dictionaries.
Fault simulation is an essential part of evaluating the testability of digital designs, and of developing test programs needed to support such designs. Often, fault simulation is not performed during the development of digital circuits, even when good circuit simulation is. Trying to develop high quality diagnostic tests without fault simulation is extremely difficult and can lead to test strategies inadequate to detect and isolate faults in complex digital designs. Therefore, investment in a commercial fault simulator and integration of fault simulation into the digital design process should be a high priority for the IPD team.10
9See RADC-TR-89-230, "Fault Simulator Evaluation," Final Technical Report, November 1989, University of South Florida
10For further information on fault simulation see: RL-TR-91-6, "Digital Logic Testing and Testability, In-House Report," February 1991, Dr. Warren H. Debany, Jr., and "Digital Systems Testing and Testable Design, Revised Edition," by Abramovici, Breuer and Friedman, IEEE Press, 1990.