Terms and abbreviation not defined elsewhere in the text of this test procedure are defined in this section.
a. Automatic Test Equipment (ATE). The apparatus with which the actual DUT will be tested. ATE includes the ability to apply a test vector sequence (see 8.1.1L).
b. Broadside application. A method of applying a test vector sequence where input stimuli change only at the beginning of a simulation cycle or ATE cycle and all changes on primary inputs of the DUT are
assumed to be simultaneous. Nonbroadside application occurs when test vectors are conditioned by additional timing information such as delay (with respect to other primary inputs), return-to-zero, return-to-one, and surround-by-complement.
c. Detection. An error at an observable primary output of a logic model caused by the existence of a logic fault. A hard detection is where an observable output value in the fault-free logic model is distinctly different from the corresponding output value in the faulty logic model. An example of a hard detection is where the fault-free logic model's output value is 0 and the faulty logic model's output value is 1, or where the fault-free logic model's output value is 1 and the faulty logic model's output value is 0. If the high-impedance state (Z) can be sensed by the ATE, then a hard detection can involve the Z state as well. A potential detection is an error where the fault-free output is 0 or 1 and the faulty output value is unknown (X), or Z if Z cannot be sensed by the ATE.
d. Established test algorithm. An algorithm, procedure, or test vector sequence, that when applied to a logic component or logic partition has a known fault coverage or test effectiveness. This fault coverage or test effectiveness is denoted herein as the established fault coverage or established test effectiveness for the established test algorithm. For example, an established test algorithm for a RAM may be a published memory test algorithm, such as GALPAT, that has been shown by experience to detect essentially all RAM failures and therefore is assessed an established test effectiveness of 100 percent. An Arithmetic Logic Unit (ALU) may be tested by means of a precomputed test vector sequence for which fault coverage has been previously determined. More than one established test algorithm may exist for a logic component or logic partition, each with a different established fault
coverage or test effectiveness.
e. Failure hierarchy: Failure mechanism, physical failure, logical fault, error. The failure hierarchy relates physical defects and their causes to fault simulators and observable effects. A failure mechanism is the actual cause of physical failure; an example is electromigration of aluminum in a microcircuit. A physical failure (or simply failure) is the actual physical defect caused by a failure mechanism; an example is an open metal line. A logical fault (or simply fault) is a logical abstraction of the immediate effect of a failure; an example is "stuck-at-one" behavior of a logic gate input in the presence of an open metal line. An error is a difference between the behavior of a fault-free and faulty DUT at one or more observable primary outputs of the DUT.
f. Fault coverage. For a
logic model of a DUT, a fault universe for the logic model of the DUT, and a
given test vector sequence, fault coverage is the fraction obtained by
dividing the number of faults contained in the fault universe that are
detected by the test vector sequence as a percentage. In this test procedure,
fault coverage is understood to be based on the detectable fault equivalence
classes (see B.184.108.40.206 ). Rounding of fault coverage fractions or percentages shall be "toward zero," not "to nearest." For example, if 9,499 faults are detected out of 10,000 faults simulated, the fault coverage is 94.99 percent; if this value is to be rounded to two significant digits, the result shall be reported as 94 percent, not 95 percent.
g. Logic line, node. Logic lines are the connections between components in a logic model, through which logic signals flow. Logic lines are the idealized "wires" in a logic model. A set of connected logic lines is a node
h. Logic: Combinational and sequential. Combinational digital logic contains only components that do not possess memory, and in which there are no feedback paths. Sequential digital logic contains at least one component that contains memory, or at least one feedback path, or both. For example, a flip-flop is a component that contains memory, and cross-coupled logic gates introduce feedback paths.
i. Macro. A logic modeling convention representing a model contained within another model. A macro boundary does not necessarily imply the existence of a physical boundary in the logic model. A main model is a logic model that is not contained within a larger model. Macros may be nested (that is, a macro may contain submacros).
j. Primary inputs, primary outputs. Primary inputs to a logic model represent the logic lines of a DUT that are driven by the ATE's drivers and thus are directly controllable test points. The inputs to the "main model" of the logic model of the DUT are the primary inputs, and the outputs from the main model are the primary outputs. Internal nodes that can be driven or sensed by means of special test nodes shall be considered to be control or observation test points.
k. Test effectiveness. A measure similar to fault coverage, but used in lieu of fault coverage in cases where physical failures cannot be modeled accurately as logical faults. For example, many RAM and Programmable Logic Array (PLA) failures cannot be idealized conveniently in the same way as gate-level failures. However, established test algorithms may be used to detect essentially all likely physical failures in such structures.
l. Test vector sequence. The (ordered) sequence of stimuli (applied to a logic model of a DUT) or stimulus/response values (applied to, and compared for, the actual DUT by the ATE).
m. Undetectable and detectable faults. An undetectable fault is defined herein as a logical fault for
which no test vector sequence exists that can cause at least one hard
detection or potential detection (see B.8.1.1c). Otherwise (that is, some test
vector sequence exists that causes at least one hard detection, or potential
detection, or both), the fault is defined herein to be a detectable fault (see