Implementation of this test procedure requires the use of a facility capable of simulating the behavior of fault-free digital logic in response to a test vector sequence; this capability is herein referred to as logic simulation.

In order to simulate sequential digital logic, the simulator must support simulation of a minimum of four logic states: zero (0), one (1), high-impedance (Z), and unknown (X). In order to simulate combinational digital logic only, the
simulator must support simulation of a minimum of two logic states: 0 and 1.

At the start of logic simulation of a logic model of a DUT containing sequential logic, the state of every logic line and component containing memory shall be X; any other initial condition, including explicit initialization of any line or memory element to a 0 or 1, shall be documented and justified in the fault simulation report.

In order to simulate wired connections or bus
structures, the simulator must be capable of resolving signal conflicts
introduced by such structures. Otherwise, modeling workarounds shall be
permitted to eliminate such structures from the logic model (see B.8.3.1.2
).

In order to simulate sequential digital logic, the simulator must support event-directed simulation. As a minimum, unit-delay logic components must be supported.

Simulation of combinational-only logic, or simulation of sequential logic in special cases (such as combinational logic extracted from a scannable sequential logic model) can be based on nonevent-directed simulation, such as levelized, zero-delay, or compiled-code methods. The fault simulation report shall describe why the selected method is equivalent to the more general event-directed method.