In addition to the capability to simulate the fault-free digital logic, the capability is also required to simulate the effect of single, permanent, stuck-at-zero and stuck- at one faults on the behavior of the logic; this capability is herein referred to as fault simulation. Fault simulation shall reflect the limitations of the target ATE. It is not necessary that the fault simulator directly support the requirements of this test procedure in the areas of hard versus potential detections, fault universe selection, and fault classing. However, the capability must exist, at least indirectly, to report fault coverage in accordance with this procedure. Where approximations arise (for example, where fault classing compensates for a different method of fault universe selection) such differences shall be documented in the fault simulation report, and it shall be shown that the approximations do not increase the fault coverage obtained.