The DUT shall be described in terms of a logic model
composed of components and connections between components. Primary inputs to
the logic model are assumed to be outputs of an imaginary component (representing the ATE's drivers), and primary outputs of the logic model are assumed to be inputs to an imaginary component (representing the ATE's comparators). Some logic simulators require that the ATE drivers and comparators be modeled explicitly; however, these components shall not be considered to be part of the logic model of the DUT.