Simple components of the logic model (logic primitives such as AND, OR, NAND, NOR, XOR, buffers, or flip-flops; generally the indivisible primitives understood by a simulator) are herein referred to as gate logic (G-logic). Complex components of the logic model (such as RAM, ROM, or PLA primitive components, and behavioral models -relatively complex functions that are treated as "black boxes" for the purpose of fault simulation) are referred to herein as block logic (B-logic).

For the purpose of fault simulation, the logic model shall be divided into nonoverlapping logic partitions; however, the entire logic model may consist of a single logic partition. The logic partitions contain components and their associated limits; although lines may span partitions, no component is contained in more than one partition. A G-logic partition contains only G-logic; any other logic is a B-logic partition.

A logic partition consisting of G-logic, or B-logic, or G-logic and B-logic that, as a unit, is testable using an established testing algorithm, with known fault coverage or test effectiveness, may be treated as a single B-logic partition.

** Figure B-10 - Node Consisting
of Fan-in Branches, a Fan-out Origin, and Fan-out
Branches**