Fault coverage reported for the logic model of a DUT shall reflect the limitations of the target ATE. Two common cases are:
a. Fault detection during fault simulation shall occur only at times where the ATE will be capable of sensing the primary outputs of the DUT; there must be a one-to- one correspondence between simulator compares and ATE compares. For example, if fault coverage for a test vector sequence is obtained using broadside fault simulation (where fault detection occurs after every change of input stimuli, including clock signals), then it is not correct to claim the
same fault coverage on the ATE if the test vectors are reformatted into cycles where a clock signal is pulsed during each cycle and compares occur only at the end of each cycle.
b. If the ATE cannot sense the Z output state (either directly or by multiple passes), then the reported fault coverage shall not include detections involving the Z state. That is, an output value of Z shall be considered to be equivalent
to an output value of X.
Any differences in format or timing of the test vector sequence, between that used by the fault simulator and that applied by the ATE, shall be documented in the fault simulation report and it shall be shown that fault coverage achieved on the ATE is not lower than the reported fault coverage.