Let "m" denote the number of logic partitions in the
logic model for the DUT. For the i th logic partition, let "Fi " denote its
fault coverage (measured in accordance with 8.3.4 ), and let " T i " denote its transistor fraction. The fault coverage "F" for the logic model for the DUT shall be calculated as:

F = F_{1}T_{1} •
F_{2}T_{2} • ... • F_{m}T_{m}

If fault simulation procedure 1 is performed for each G-logic partition in the logic model of a DUT, then the fault coverage for the logic model of a DUT shall be reported as:

F of all detectable equivalence classes of single, permanent, stuck-at-zero and stuck-at-one faults on the logic lines of the logic model as measured by MIL-STD-883, test method 5012."

If fault simulation procedure 2 or 3 is performed for any G-logic partition, then the fault coverage for the logic model of a DUT shall by reported as:

"No less than F of all detectable equivalence classes of single, permanent, stuck-at-zero and stuck-at-one faults on the logic lines of the logic model, with 95 percent confidence, as measured by MIL-STD-883, test method 5012"

The confidence level of 95 percent shall be identified if any fault simulation procedure other than procedure 1 was performed for any G-logic partition.