Many of the testability and diagnostics guidelines in Sections C-3 and C-4 have been excerpted from RL-TR-92-12, TESTABILITY DESIGN GUIDE RATING SYSTEM: Testability Handbook, dated February 1992. In addition, that document provides the following general guidance regarding testability and diagnostics.
Redundancy -Built-in-Test (BIT) can be implemented by repeating the functional circuitry (the redundancy) to be tested by BIT. The same functional signal(s) is input into the redundant element and Circuit Under Test (CUT). Therefore, the circuitry of the CUT exists twice in the design and the outputs can be compared. If the output values are different and their difference exceeds a limit (analog circuits), then a fault exists. Due to the expense of this technique, redundant BIT design is usually implemented only in critical functions
An example of a BIT design using redundancy is shown in Figure C-1. In this example, an analog circuit is repeated and the difference between the output levels is compared. If the difference exceeds a predefined threshold, then a fault signal is generated and latched.
Figure C-1 - Redundancy BIT (source: RADC-TR-89-209, Vol. II)
Wrap-around BIT -Wrap-around BIT requires and tests microprocessors and their input and output devices. During test, data leaving output devices is routed to input devices of the module. The BIT routine is stored in on-board read-only memory (ROM). Wrap-around can be done by directing output signals from the processor back to the input signals and verifying the input signal values. Wrap-around BIT can be applied to both digital and analog signals concurrently. An example of wrap-around BIT testing both analog and digital devices is shown in Figure C-2. In this example, during normal operation processor outputs are converted from digital to analog outputs and analog inputs are converted to digital input signals. When the BIT is initiated, the analog outputs are connected to the analog inputs and the signals are verified by the processor.
Figure C-2 - Wrap-around BIT (source: RADC-TR-89-209, Volume II)
The remainder of RL-TR-92-12, Volume I, provides detailed guidance on testability design techniques and structured test techniques for the categories of part types and technologies shown in Table C-III on the following page.
Table C-IV - Inherent Testability Checklist
Mechanical Design Checklist (for electronic designs)
- Is a standard grid layout used on boards to facilitate identification of components?
- Are the number of I/O pins in an edge connector or cable connector compatible with the I/O capabilities of the selected test equipment?
- Are connector pins arranged such that the shorting of physically adjacent pins will cause minimum damage?
- Is the design free of special set-up requirements (special cooling) which would slow testing?
- Does the item warm up in a reasonable amount of time?
- Has provision been made to incorporate a test-header connector into the design to enhance ATE testing of surface-mounted devices?
- Is defeatable keying used on each board so as to reduce the number of unique interface adapters required?
- Is each hardware component clearly labeled?
- Are all components oriented in the same direction (pin 1 always in same position)?
- Does the board layout support guided-probe testing techniques?
- When possible, are power and ground included in the I/O connector or test connector?
- Have test and repair requirements impacted decisions on conformal coating?
- Is enough spacing provided between components to allow for clips and test probes?
|Partitioning Checklist (for electronic functions) |
- Is each function to be tested placed wholly upon one board?
- Within a function, is the size of each block of circuitry to be tested small enough for economical fault detection and isolation?
- Is the number of power supplies required compatible with the test equipment?
- If more than one function is place on a board, can each be tested independently?
- If required, are pull up resistors located on same board as the driving component?
- Is the number and type of stimuli required compatible with the test equipment?
- Within a function, can complex digital and analog circuitry be tested independently?
- Are analog circuits partitioned by frequency to ease tester compatibility?
- Are elements which are included in an ambiguity group placed in the same package?
|Test Control Checklist
- Are connector pins not needed for operation used to provide test stimulus and control from the tester to internal nodes?
- Is it possible to disable on-board oscillators and drive all logic using a tester clock?
- Is circuitry provided to by-pass any (unavoidable) one-shot circuitry?
- In microprocessor-based systems, does the tester have access to the data bus, address bus and important control lines?
- Are active components, such as demultiplexers and shift registers, used to allow the tester to control necessary internal nodes using available input pins?
- Can circuitry be quickly and easily driven to a known initial state? (master clear, less than N clocks for initialization sequence)?
- Can long counter chains be broken into smaller segments in test mode with each segment under tester control?
- Can feedback loops be broken under control of the tester?
- Are test control points included at those nodes which have high fan-in (test bottlenecks)?
- Are redundant elements in design capable of being independently tested?
- Can the tester electrically partition the item into smaller independent, easy-to-test segments? (placing tri-state element in a high impedance state).
- Have provisions been made to test the system bus as a stand-alone entity?
- Are input buffers provided for those control point signals with high drive capability requirements?
|Parts Selection Checklist |
- Is the number of different part types the minimum possible?
- Is a single logic family being used? If not, is a common signal level used for interconnections?
- Have parts been selected which are well characterized in terms of failure modes?
- Are the parts independent of refresh requirements? If not, are dynamic devices supported by sufficient clocking during testing?
- Are unused connector pins used to provide additional internal node data to the tester?
- Are test access points placed at those nodes which have high fan-out?
- Are active components, such as multiplexers and shift registers, used to make necessary internal node test data available to the tester over available output pins?
- Are signal lines and test points designed to drive the capacitive loading represented by the test equipment? ¥ Are buffers employed when the test point is a latch and susceptible to reflections?
- Are all high voltages scaled down within the item prior to providing test point access so as to be consistent with tester capabilities?
- Are test points provided such that the tester can monitor and synchronize to onboard clock circuits?
- Are buffers or divider circuits employed to protect those test points which may be damaged by an inadvertent short circuit?
- Is the measurement accuracy of the test equipment adequate compared to the tolerance requirement of the item being tested?
Analog Design Checklist
- Is one test point per discrete active stage brought out to the connector?
- Are circuits functionally complete without bias networks or loads on some other UUT?
- Is a minimum number of complex modulation or unique timing patterns required?
- Are response rise time or pulse width measurements compatible with test capabilities?
- Does the design avoid or compensate for temperature sensitive components?
- Is each test point adequately buffered or isolated from the main signal path?
- Is a minimum number of multiple phase-related or timing-related stimuli required?
- Are stimulus frequencies compatible with tester capabilities?
- Are stimulus amplitude requirements within the capability of the
- Does the design allow testing without heat sinks?
- Are multiple, interactive adjustments prohibited for production items?
- Is a minimum number of phase or timing measurements required?
- Do response measurements involve frequencies compatible with tester capabilities?
- Does the design avoid external feedback loops?
- Are standard types of connectors used?
RF Design Checklist
- Do transmitter outputs have directional couplers or similar signal sensing/attenuation techniques employed for BIT or off-line test monitoring purposes, or both?
- Has provision been made in the off-line ATE to provide switching of all RF stimulus and response signals required to test the subject RF UUT?
- Are the RF test input/output access ports of the UUT mechanically compatible with the off-line ATE I/O ports?
- Have adequate testability (controllability/ observability) provisions for calibrating the UUT been provided?
- If an RF transmitter is to be tested utilizing off-line ATE, has suitable test fixturing (anechoic chamber) been designed to safely test the subject item over its specified performance range of frequency and power?
- Have all RF testing parameters and quantitative requirements for these parameters been explicitly stated at the RF UUT interface for each RF stimulus/
response signal to be tested?
- Has the UUT/ATE RF interface been designed so that the system operator can quickly and easily connect and disconnect the UUT without special tooling?
- Have RF compensation procedures and data bases been established to provide calibration of all stimulus signals to be applied and all response signals to be measured by BIT or off-line ATE to the RF UUT interface?
- Have suitable termination devices been employed in the off-line ATE or BIT circuitry to accurately emulate the loading requirements for all RF signals to be tested?
- Does the RF UUT employ signal frequencies or power levels in excess of the core ATE stimulus/ measurement capability? If so, are signal converters employed within the ATE to render the ATE/UUT compatible?
- Has the RF UUT been designed so that repair or replacement of any assembly or subassembly can be accomplished without major disassembly of the unit?
- Does the off-line ATE or BIT diagnostic software provide for compensation of UUT output power and adjustment of input power, so that RF switching and cable errors are compensated for in the measurement data?
Electro-optical (EO) Design Checklist
- Have optical splitters/couplers been incorporated to provide signal accessibility without major disassembly?
- Has temperature stability been incorporated into fixture/UUT design to assure consistent performance over a normal range of operating environments?
- Have optical systems been functionally allocated so that they and associated drive electronics can be independently tested?
- Are the ATE system, light sources, and monitoring systems of sufficient wave-length to allow operation over a wide range of UUTs?
- Does the test fixturing intended for the off-line test present the required mechanical stability?
- Is there sufficient mechanical stability and controllability to obtain accurate optical registration?
- Can requirements for boresighting be automated or eliminated?
- Do monitors possess sufficient sensitivity to accommodate a wide range of intensities?
- Can optical elements be accessed without major disassembly or realignment?
- Do they possess sufficient range of motion to meet a variety of test applications?
- Has adequate filtering been incorporated to provide required light attenuation?
- Can all modulation models be simulated, stimulated, and monitored?
- Can targets be automatically controlled for focus and aperture presentation?
- Do light sources provide enough dynamics over the operating range?
- Do test routines and internal memories test pixels for shades of gray?
- Are optical collimators adjustable over their range of motion via automation?
Digital Design Checklist
- Does the design contain only synchronous logic?
- Does the design avoid resistance capacitance one-shots and dependence upon logic delays to generate timing pulses?
- Is the design free of WIRED-ORs?
- Will the selection of an unused address result in a well defined error state?
- Are all clocks of differing phases and frequencies derived from a single master clock?
- Is the number of fan-outs for each board output limited to a predetermined value?
- Are latches provided at the inputs to a board in those cases where tester input skew could be a problem?
- For multilayer boards, is the layout of each major bus such that current probes or other techniques may be used for fault isolation beyond the node?
- If the design incorporates a structured testability design technique (scan path, signature analysis), are all the design rules satisfied?
- Is the number of fan-outs for each internal circuit limited to a predetermined value?
- Are all memory elements clocked by a derivative of the master clock? (Avoid elements clocked by data from other elements.)
- Does the design include data wrap-around circuitry at major interfaces?
- Is a known output defined for every word in a read only memory?
- Are sockets provided for microprocessors and other complex components?
- Does the design support testing of "bit slices"?
- Do all buses have a default value when unselected?
Built-in-Test (BIT) Checklist
- Can BIT in each item be exercised under control of the test equipment?
- Does the BIT use a building-block approach (all inputs to a function are verified before that function is tested)?
- Does on-board ROM contain self-test routines?
- Does BIT include a method of saving on-line test data for the analysis of intermittent failures and operational failures which are non-repeatable in the maintenance environment?
- Is the additional volume due to BIT within stated constraints?
- Does the allocation of BIT capability to each item reflect the relative failure rate of the items and the criticality of the items' functions?
- Are the data provided by BIT tailored to the differing needs of the system operator and the system maintainer?
- Is the failure latency associated with a particular implementation of BIT consistent with the criticality of the function being monitored?
- Is the test program set designed to take advantage of BIT capabilities?
- Does building-block BIT make maximum use of mission circuitry?
- Is the self-test circuitry designed to be testable?
- Is the predicted failure rate contribution of the BIT circuitry within stated constraints?
- Is the additional power consumption due to BIT within stated constraints?
- Are BIT threshold values, which may require changing as a result of operational experience, incorporated in software or easily-modified firmware?
- Are on-board BIT indicators used for important functions?
- Are BIT indicators designed such that a BIT failure will give a "fail" indication?
Built-in-Test (BIT) Checklist (continued)
- Is sufficient memory allocated for confidence tests and diagnostic software?
- Are BIT threshold limits for each parameter determined as a result of considering each parameter's distribution statistics, the BIT measurement error and the optimum fault detection/false alarm characteristics?
- Is BIT optimally allocated in hardware, software, and firmware?
- Have means been established to identify whether hardware or software has caused a failure indication?
- Is the additional weight due to BIT within stated constraints?
- Is the additional part count due to BIT within stated constraints?
- Is processing or filtering of BIT sensor data performed to minimize BIT false alarms?
- Does mission software include sufficient hardware error detection capability?
Performance monitoring Checklist
- Have critical functions been identified (by FMECA) which require monitoring for the system operation and users?
- Have interface standards been established that ensure the electronic transmission of data from monitored systems is compatible with centralized monitors?
- Has the displayed output of the monitoring system received a human engineering analysis to ensure that the user is supplied with the required information in the best useable form?
Diagnostic Capability Integration
- Have vertical testability concepts been established, employed, and documented?
- Has the diagnostic strategy (dependency charts, logic diagrams) been documented?
- Has a means been established to ensure compatibility of testing resources with other diagnostic resources at each level of maintenance (technical information, personnel, and training)?
Mechanical Systems Condition Monitoring (MSCM) Checklist
- Have MSCM and battle damage monitoring functions been integrated with other performance monitoring functions?
- Are preventive maintenance monitoring functions (oil analysis, gear box cracks) in place?
- Have scheduled maintenance procedures been established?
- Are pressure sensors placed very close to pressure sensing points to obtain wideband dynamic data?
- Has the selection of sensors taken into account the environmental conditions under which they will operate?
- Have procedures for calibration of sensing devices been established?
- Has the thermal lag between the test media and sensing elements been considered?
Test Requirements Checklist
- Has a "level of repair analysis" been accomplished?
- For each maintenance level, has a decision been made for each item on how BIT, ATE, and General Purpose Electronic Test Equipment (GPETE), will support fault detection and isolation?
- For each item, does the planned degree of testability design support the level of repair, test mix, and degree of automation decisions?
- Is the planned degree of test automation consistent with the capabilities of the maintenance technician?
Test Data Checklist
- Do state diagrams for sequential circuits identify invalid sequences and indeterminate outputs?
- For computer-assisted test generation, is the available software sufficient in terms of program capacity, fault modeling, component libraries, and post-processing of test response data?
- If a computer-aided design system is used for design, does the CAD data base effectively support the test generation process and test evaluation process?
- Is the tolerance band known for each signal on the item?
- Are testability features included by the system designer documented in the Test Requirement Document (TRD) in terms of purpose and rationale for the benefit of the test designer?
- For large scale ICs used in the design, are data available to accurately model the circuits and generate high-confidence tests?
- Are test diagrams included for each major test? Is the diagram limited to a small number of sheets? Are inter-sheet connections clearly