Are unused connector pins used to provide additional internal node
data to the tester?
Are signal lines and test points designed to drive the capacitive
loading represented by the test equipment?
Are test points provided such that the tester can monitor and
synchronize to onboard clock circuits?
Are test access points pieced at those nodes which have high
Are buffers employed when the test point is a latch and susceptible
Are buffers or divider circuits employed to protect those test points
which may be damaged by an inadvertent short circuit?
Are active components, such as muitiplexers and shift registers, used
to make necessary internal node test data available to the tester over
available output pine?
Are all high voltages scaled down within the item prior to providing
test point access so as to be consistent with tester capabilities?
Is the measurement accuracy of the test equipment adequate compared
to the tolerence requirement of the item being tested?