Does the design contain only synchronous logic?
Are all clocks of differing phases and frequencies derived from a
single master clock?
Are all memory elements clocked by a derivative of the master clock?
(Avoid alements clocked by data from other elements.)
Does the design avoid resistance capacitance one-shots and dependence
upon logic delays to generate timing pulses?
Does the design support testing of “bit slices"?
Does the design include data wraparound circuitry at major
Do all buses have a default value when unselected?
For multilayer boards, is the layout of each major bus such that
current probes or other techniques may be used for fault isolation
beyond the node?
Is a known output defined for every word in a Reed Only Memory (ROM)?
Will the improper selection of an unused address result in a well
defined error state?
Is the number of fan-outs for each internal circuit limited to a
Is the number of fan-outs for each board output limited to a
Are latches provided at the inputs to a board in those cases where
tester input skew could be a problem?
Is the design free of WIRED-ORs?
Does the design include current limiters to prevent domino effect
If the design incorporates a structured testability design technique
(e.g., Scan Path, Signature Analysis), are all the dasign rules
Are sockets provided for microprocessors and other comples