Built-In Test (BIT)
Can BIT in each item be exercised under control of the test
Is the Test Program Set designed to take advantage of BIT
Are on-bard BIT indicators used for important functions? Are BIT
indicators designed such that a BIT failure will give a FAIL
Does the BIT use a building-block approach (e.g., all inputs to a
function are verified before that function is tested)?
Does building-block BIT make maximum use of mission circuitry?
Is BIT optimally allocated in hardware, software and firmware?
Does on-board ROM contain self-test routines?
Does BIT include a method of saving on-line test data for the
analysis of intermittent failures and operational failures which are
non-repeatable in the maintenance environment?
Is the failure rate contribution of the BIT circuitry within stated
Is the additional weight attributed to BIT within stated
Is the additional volume attributed to BIT within stated
Is the additional power consumption attributed to BIT within stated
Is the additional part count due to BIT within stated
Does the allocation of BIT capability to each item reflect the
relative failure rate of the items and the criticality of the itemsí
Are BIT threshold values, which may require changing as a result of
operational experience, incorporated in software or easily-modified
Is processing or filtering of BIT sensor data performed to minimize
BIT false alarms?
Are the data provided by BIT tailored to the differing needs of the
system operator and the system maintainer?
Is sufficient memory allocated for confidence tests and diagnostic
Does mission software include sufficient hardware error detection
Is the failure latency associated with a particular
implementation of BIT consistent with the criticality of the function
Are BIT threshold limits for each parameter
determined as a result
each parameterís distribution statistics,
measurement error and the
optimum fault detection/false alarm