For a complete and accurate sneak analysis, the data on all system hardware
and software must be reviewed and partitioned. This assures that a potential
sneak condition is not inadvertently overlooked because of inaccurate,
incomplete, or missing data.
The data review assures that the data represent the complete system and are
of the appropriate level of detail. For the hardware, each component and its
connectivity within the system must be described. The level of detail required
for software is a documented listing of the source program. The electrical
interface at each integrated circuit must be shown. If insufficient detail is
provided, e.g., functional blocks only, the analysis would be reduced merely to
verifying the system interface which is usually well defined and checked by
other means. Therefore, detailed schematics, wire listings, and other data are
reviewed to assure that the required level of detail and its "as-built"
representation is known.
The system data are partitioned to replace the complex interconnected system
data with multiple subsets (network trees). This process involves applying
specific partitioning rules to the hardware and software data. The network trees
developed typically have a single output cross-referenced to all related inputs.
At the various partition points, special codes are assigned which permit system
connectivity to be maintained through computer-generated cross-references based
on those codes.
Partitioning in software is based on subroutines and identifying subfunctions
within large subroutines. Most small subroutines will become a single network
tree. Large subroutines may become several network trees based on the
subfunctions within the routine.
For purposes of this example, only the portion of the weapon controller
schematics that details circuit card No. 9431A2A2 will be required. This
schematic is shown in Figure A-7. In addition to the circuitry, Figure A-7
also shows the required partitioning and partition codes which maintain
connectivity. Figure A-8 shows how the circuitry is split and regrouped after
partitioning. The portion of each figure enclosed in broken lines is the
circuitry of interest in this example. It will be designated later as Nodal