This section lists some of the clues associated with parts and
configurations that will assist the analyst in detecting sneak
It is also important to recall that in performing an SCA, the analyst will
develop a detailed understanding of the portions of the system being
evaluated. The fairly rigorous engineering analysis required for the SCA often
leads to the uncovering of other problems unrelated to sneak circuits.
Detecting these conditions, termed Design Concerns, represents a significant
collateral benefit of the analysis and should not be disregarded by the
For this reason, the list of clues also includes a sampling of conditions
that the analyst should be sensitive to during the SCA. Observation of such
conditions should result in the reporting of the Design Concerns to the
appropriate organization. The clues not directly related to sneak conditions
are marked with an asterisk(*).
The listing of clues is not intended to be exhaustive; it is, however, a
relatively comprehensive sample.
a. Determine charging and discharging time
b. Are undesired discharge paths possible?
c. Does an
undesired voltage supply exist via discharge?
*d. Is the maximum possible
voltage within derating criteria?
*e. Could maximum charge/discharge
currents damage other components?
*f. Are reverse voltages present when
tantalum capacitors are used?
*g. Does the available energy
meet or exceed the desired level?
a. Do suppression diodes allow for proper current flow at the proper time?
Also, has suppression usage caused timing problems?
b. Does the I2 t curve
indicate any necessary turn-on delays?
c. Does forward resistance of the
diode affect charging and discharging times? Check capacitive and inductive
*d. Is the maximum forward current within
*e. In the presence
of high temperatures, will redundancy cause unequal loads?
III. Integrated Circuits (ICs)
*a. Are inputs properly biased?
*b. Verify that Vin is less than Vcc for
*c. Are transients filtered and/or suppressed?
voltage and output current within derating criteria?
*e. Does the component
have the proper "fan-in/ fan-out" parameters?
*f. Are unused inputs tied
*g. Check for
IV. Power Sources and Ground
a. Verify power ground tied to signal return. Does the proper isolation
resistance exist between them?
b. Verify that digital circuits, squibs, and
relays are not on same ground.
c. Verify that chassis ground tied to signal
d. Does the proper resistance and potential difference exist
between tied power sources?
e. Is diode blocking used to stop power
f. Verify that battery power supply and generator
ground are at the same reference point.
V. Relay Coils :
Relay, Motors, Inductive
a. Has two-diode input and suppression been examined for unexpected
configuration prevents reverse voltage burnout, timing problems may result.
The forward resistance of D1 is very low; thus the time constant ( = L/R) is large and
the time delay is increased by a factor of five to ten .]
*b. Is proper suppression incorporated?
*c. Has reverse voltage burnout
been considered in single-diode usage?
*d. Do actual
voltage and current measurements compare with manufacturer's
a. Have derated current and wattage ratings been
compared with pulse watt/time charts?
VII. Operational Amplifiers (Op-Amps)
*a. Are suitable bias current resistors of proper values
*b. Have unused Op-Amps been
put into a unity gain configuration with all inputs grounded?
VIII. Silicon Controlled Rectifiers
a. Turn-on occurs in the presence of a
short-duration, low-valued gate current. However, once on, the SCR is
difficult to drive off. Does such a low-valued current exist as a sneak
a. Has delay time been considered during design?
b. After firing, can
the component short or open?
c. During check-out test, is "no-fire" current
*d. Is the available energy sufficient to "blow"
*e. Has static energy protection been provided?
*f. Can a
short-circuit in a squib damage other circuit components? (Capacitor voltage
discharge sources are not as likely to burn a squib "open as is a battery or
*g. Have current limiting resistors been
*h. Have redundancy and
range safety requirements been met?
a. Check maximum "break/make" times.
b. Has the timing of switches,
especially those that are relay controlled. manually controlled or squib
fired, been considered during design?
*c. Do maximum currents exceed
allowable derated values?
*d. Check maximum "break/make" current
*e. Has redundancy been
a. Have turn-on/turn-off times been considered during design?
transistor properly biased?
c. Do active base current and saturated
collector current meet derating specification?
collector/base voltages within derating criteria?
XII. Transistor-Transistor Logic (TTL) Devices
a. Does high output impedance cause slow operation (long RC time
b. Are there ground paths to inputs (momentary or otherwise)
which will turn device on?
*c. Does an open collector interface with a
device which does not have a pull-up resistor?
*d. Are "fan-in/fan-out"
allowed loading (impedances) exceeded?
*e. Is sufficient current limiting
provided in ground-to-output?
*f. Are unused inputs/gates terminated to Vcc
or other biasing voltage in order to minimize input coupling capacitance and
*g. Is minimum noise margin of 0.5V at inputs for LS-type
logic maintained (i.e., input at least 0.5V above minimum allowed)?