Peak Instantaneous Transients and Subtleties
The most predominant power supply failure modes are caused by peak
instantaneous transients and subtle factors within and external to the power
supply. Sneak circuits and built-in wear-out mechanisms must be considered in
the design and packaging of the power supply system. Sneak circuits are
addressed in Department of the Navy document NAVSO P-3634.
Hostile environments such as temperature, shock, vibration, altitude and
humidity accelerate failure modes.
Training engineers, designing with margin, incorporating protective
circuits, performing worst-case analysis and conducting comprehensive testing
to prove the design are musts to achieve power supply reliability and
Use of MIL-HDBK-217
Many designers consider only static conditions and do not address transient
conditions such as transistor load line variations and various peaks and
surges as well as items such as capacitor core temperature.
Be cautious of a simple and inexpensive switching-mode
power supply with a high predicted MTBF determined in accordance with
MIL-HDBK-217. See Reference 30
. The expected MTBF of power supplies designed and manufactured in
accordance with the guidelines presented herein will exceed predictions per
MIL-STD-756, Method 2005, using MIL-HDBK-217.
These predictions can be used to identify internal component reliability
concerns and also identify the lower limit of expected MTBF performance. These
predictions should not be used as a basis for setting contractual reliability
requirements, but should focus on operational mission and system
Points to Consider
The following is a list of key points to consider when designing and
evaluating a switching-mode power supply design:
(1) Incorporate voltage transient protection on the input power
(2) Include a controllable soft-start circuit to relieve the component
stresses during turn-on.
(3) Build an internal housekeeping power supply to isolate sensitive
circuits from the hostile power line, improve human safety and allow control
of the power-up and power-down cycles.
(4) Tailor the turn-on and turn-off
load lines to minimize peak power in the semiconductors during power supply
(5) Incorporate a crossover interlock circuit in the power stage that is
connected across the power line so that two devices can never conduct
simultaneously across the power line.
(6) Incorporate input EMI filtering having characteristics compatible with
the negative resistance of the power supplies and variable input source
impedances so that the combination is stable.
(7) Incorporate a fast-attack current limiting circuit to protect the power
devices when the control logic "glitches" due to random noise or other
(8) Design the power inductors, transformers and magnetics to keep them out
of saturation during peak load and transient conditions.
(9) Sequence the turn-on/turn-off logic in an orderly and controllable
(10) Analyze and measure worst-case peak currents, peak power, peak voltage
and ripple currents in all devices and under all worst-case static and dynamic
conditions. Compare the measured results with the rated limits of all
(11) Perform worst-case thermal and hot-spot analyses.
(12) Design printed wiring boards and packaging for the best heat transfer.
Plan the circuit so that it will not be subject to common-mode and
differential-mode noise. Circuit design engineers must be responsible for the
electrical and printed wiring board layouts.
(13) Package magnetic devices and other heavy-current-carrying conductors
with thermal interfaces adequate to meet hot-spot temperature
(14) Avoid ground loops and potential cross-talk and interaction by
developing a grounding technique that is appropriate to the
(15) Analyze and measure loop stability to ensure that there is adequate
phase and gain margin under all line, load, temperature and component