In the design of MIBs, several electrical parameters must be
controlled to assure proper functioning of the finished module. The electrical
considerations affecting the circuit performance are the product of individual
design requirements and the manufacturing process used to produce the MIB.
Only general guidelines can be offered here since many factors such as
frequency, rise time, fan out, and generic IC series will determine final
There are, however, factors affecting circuit performance over
which the MIB designer can exercise control, and guidelines are offered in
four major areas: crosstalk, capacitive loading, resistance, and power
Crosstalk is the undesirable coupling of energy between
conductor traces. This unwanted transfer results from capacitive and inductive
coupling and can produce false triggering in passive conductors when adjacent
active conductors are pulsed. Inductance in MIBs is generally low. Capacitance
on the other hand can be quite high due to the high dielectric constant of
ceramic and the small physical separation between individual conductors, and
between conductive layers. Capacitance in MIBs is a function of dielectric
constant, conductor area, and the dielectric thickness between conductors.
Reducing capacitance between traces through any of these factors will reduce
The dielectric constant of a thick film paste has a direct
effect on circuit impedance and operating speed. The dielectric pastes
associated with copper have a dielectric constant of 6 to 8. Noble metal
dielectric pastes range between 8 and 10. The dielectric constant for a given
paste cannot be altered. Selection of a dielectric paste having the lowest
dielectric constant consistent with processing needs will lower
Increased dielectric thickness between signal layers as well as
between signal layers and the ground layer will reduce capacitance/crosstalk.
Double or triple screen-dry-fired dielectric is commonly used between signal
layers to reduce the incidence of pinhole shorts through the dielectric as
well as to reduce capacitance. Increases in dielectric thickness beyond triple
screenings will result in increased costs, but this may be offset by higher
yields, especially in large boards.
One notable exception to reduced capacitance should be noted. It
is often desirable to have capacitive coupling between the ground plane and
the voltage plane. For this reason, it may be desirable to place the voltage
layer on the MIB base first, followed by the ground layer, with a minimum of a
double dielectric screening thickness for pin-hole short circuit protection.
Since power and ground planes are both generally large areas, there is a
higher probability of a short developing between them during processing than
between any other pairs of layers. From a producibility standpoint it would be
desirable to leave greater than normal spacing (more dielectric layers)
between them. The designer must determine the resolution of this conflict
between electrical performance and producibility.
Conductor spacing is usually limited by the manufacturing
process as well as the desire to maximize component mounting area. Crosstalk
reduction will result from the use of the largest conductor spacing practical.
In most applications, lines are not specified to be spaced closer than on
0.020-inch centers. For example, the space between two 0.008-inch-wide
adjacent conductors would nominally be
CAPACITIVE LOADING AND CONDUCTOR ROUTING
Capacitive loading is a detrimental factor when implementing
controlled impedance circuits. Small capacitive loads are added throughout the
length of the line as it crosses over other conductors and traverses different
layers. This increases the line capacitance and reduces the impedance of the
signal path, adversely affecting circuit performance. Control of conductor
routing can be used to reduce capacitive loading.
Signal conductors on one layer should be routed in the same
direction and parallel to a MIB edge. Conductors at right angles should be
kept as short as possible. Adjacent layer signal conductors should be routed
perpendicular to each other and staggered to prevent conductor overlap.
Conductor widths as small as practical within process and resistance
limitations will also help to substantially reduce the conductor plate area
for reduced capacitance loading.
The fired thickness of a thick film conductor is nominally
0.0005 inch. The width of the conductor must be specified with respect to the
resistivity of the conductor material to control the resistance of the circuit
lines. In a copper thick film system, the line resistivity is approximately
two milliohms per square, resulting in a resistance for a 0.008-inch-wide line
of 250 milliohms per inch. Since the resistivity of the noble metal system is
slightly higher, the width of the line should be 0.010 inch to be equivalent
to the copper system.
Resistance of the conductors in the voltage plane and the
ground plane decreases the supply voltage to a chip. The voltage tolerance at
the chip level is commonly ± 10%. The width of the conductors on the voltage plane
and the ground plane must be maximized to reduce the voltage drop, but must
also be kept within producibility guidelines.
POWER DENSITY LIMITS DUE TO THERMAL TRANSFER
The number and location of components placed on a MIB not only
will be a function of the physical sizes of the components but also will
depend on the overall thermal design of the system and the thermal
requirements imposed on the system by the environment. When the partitioning
of the system is firm, the placement of components on the circuit board should
be determined with consideration given to the optimum thermal layout of the
board. If this decision process is implemented during circuit routing, ideal
tradeoffs can probably be obtained. For detailed information on power
considerations in MIB design, refer to Thermal Considerations in this