• Route time-critical signals on the top interconnect layers,
far from the ground planes to minimize capacitance.
• Keep line width dimensions to a minimum consistent with
producibility and dc resistance constraints.
• Alternate the horizontal and vertical interconnect patterns on
successive layers to minimize crosstalk.
• Minimize routing of interconnect lines next to a row of vias
or over vias to reduce the possibility of shorts.
• Stagger the vias when interconnecting through more than four
conductive layers (three vias--see Figure 4-8) to minimize the possibility of
cracks on the top layers.